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CY7C1021CV33
1-Mbit (64K x 16) Static RAM
Features
Functional Description
The CY7C1021CV33 is a high performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO1 through IO8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from IO pins (IO9 through IO16) is written into the location specified on the address pins (A0 through A15). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO1 to IO8. If Byte High Enable (BHE) is LOW, then data from memory appears on IO9 to IO16. For more information, see the "Truth Table" on page 9 for a complete description of Read and Write modes. The input and output pins (IO1 through IO16) are placed in a high impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW). For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Temperature ranges Commercial: 0C to 70C Industrial: -40C to 85C Automotive-A: -40C to 85C Automotive-E: -40C to 125C Pin and function compatible with CY7C1021BV33 High speed tAA = 8 ns (Commercial) tAA = 10 ns (Industrial and Automotive-A) tAA = 12 ns (Automotive-E) CMOS for optimum speed and power Low active power: 325 mW (max) Automatic power down when deselected Independent control of upper and lower bits Available in Pb-free and non Pb-free 44-pin 400 Mil SOJ, 44-pin TSOP II and 48-Ball FBGA packages

Logic Block Diagram
DATA IN DRIVERS
A7 A6 A5 A4 A3 A2 A1 A0
ROW DECODER
64K x 16 RAM Array
SENSE AMPS
IO0-IO7 IO8-IO15
COLUMN DECODER
BHE WE CE OE BLE
Cypress Semiconductor Corporation Document Number: 38-05132 Rev. *I
*
A8 A9 A10 A11 A12 A13 A14 A15
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised January 04, 2008
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CY7C1021CV33
Selection Guide
Description Maximum Access Time Maximum Operating Current Commercial Industrial Automotive-A Automotive-E Maximum CMOS Standby Current Commercial Industrial Automotive-A Automotive-E 5 5 5 5 5 10 -8 8 95 -10 10 90 90 90 90 5 5 5 5 -12 12 85 85 80 -15 15 80 Unit ns mA mA mA mA mA mA mA mA
Pin Configuration
Figure 1. 44-Pin SOJ/TSOP II [1] Figure 2. 48-Ball FBGA Pinout [1]
A4 A3 A2 A1 A0 CE IO1 IO2 IO3 IO4 VCC VSS IO5 IO6 IO7 IO8 WE A15 A14 A13 A12 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
A5 A6 A7 OE BHE BLE IO16 IO15 IO14 IO13 VSS VCC IO12 IO11 IO10 IO9 NC A8 A9 A10 A11 NC
1 BLE IO8 IO9 VSS VCC IO14 IO15 NC
2 OE BHE IO10 IO11 IO12 IO13 NC A8
3 A0 A3 A5 NC NC A14 A12 A9
4 A1 A4 A6 A7 NC A15 A13 A10
5 A2 CE IO2 IO3 IO4 IO5 WE A11
6 NC IO0 IO1 VCC VSS IO6 IO7 NC A B C D E F G H
Note 1. NC pins are not connected on the die.
Document Number: 38-05132 Rev. *I
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CY7C1021CV33
Pin Definitions
Pin Name A0-A15 SOJ, TSOP Pin Number BGA Pin Number IO Type Input Description Address Inputs. Used to select one of the address locations.
1-5, 18-21, A3, A4, A5, B3, 24-27, 42-44 B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4
IO1-IO16 [2]
7-10, 13-16, B6, C6, C5, Input or Output Bidirectional Data IO lines. Used as input or output lines depending on operation. 29-32, 35-38 D5, E5, F5, F6, G6, B1, C1, C2, D2, E2, F2, F1, G1 22, 23, 28 17 6 40, 39 41 A6, D3, E3, E4, G2, H1, H6 G5 B5 B2, A1 A2 No Connect Input or Control Input or Control Input or Control Input or Control No Connects. Not connected to the die. Write Enable Input, Active LOW. When selected LOW, a write is conducted. When deselected HIGH, a read is conducted. Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. Byte Write Select Inputs, Active LOW. BHE controls IO16 - IO9, BLE controls IO8 - IO1. Output Enable, Active LOW. Controls the direction of the IO pins. When LOW, the IO pins are allowed to behave as outputs. When deasserted HIGH, the IO pins are tri-stated and act as input data pins. Ground for the Device. Connected to ground of the system.
NC WE CE BHE, BLE OE
VSS VCC
12, 34 11, 33
D1, E6 D6, E1
Ground
Power Supply Power Supply Inputs to the Device.
Note 2. IO1-IO16 for SOJ/TSOP and IO0-IO15 for BGA packages.
Document Number: 38-05132 Rev. *I
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CY7C1021CV33
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VCC Relative to GND[3] .....-0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[3] ...................................... -0.5V to VCC+0.5V DC Input Voltage[3] .................................. -0.5V to VCC+0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (MIL-STD-883, Method 3015) Latch Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Automotive-A Automotive -E Ambient Temperature (TA) 0C to +70C -40C to +85C -40C to +85C -40C to +125C VCC 3.3V 10%
Electrical Characteristics
Over the Operating Range Parameter VOH VOL VIH VIL IIX Description Test Conditions -8 Min 2.4 0.4 2.0 -0.3 GND < VI < VCC Commercial Industrial Automotive-A Automotive-E IOZ Output Leakage Current GND < VI < VCC, Output disabled Commercial Industrial Automotive-A Automotive-E ICC VCC Operating Supply Current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC Commercial Industrial Automotive-A Automotive-E ISB1 Automatic CE Power Max VCC, Down Current --TTL CE > VIH Inputs VIN > VIH or VIN < VIL, f = fMAX Commercial Industrial Automotive-A Automotive-E ISB2 Automatic CE Power Max VCC, Commercial Down Current -- CE > VCC - 0.3V, Industrial CMOS Inputs VIN > VCC - 0.3V, or VIN < 0.3V, f = 0 Automotive-A Automotive-E 5 5 5 5 10 15 15 15 15 20 5 5 5 5 mA 95 90 90 90 90 15 15 15 15 mA -1 +1 -1 -1 -1 +1 +1 +1 -12 +12 85 85 80 80 mA -1 VCC + 0.3 0.8 +1 2.0 -0.3 -1 -1 -1 Max 2.4 0.4 VCC + 0.3 0.8 +1 +1 +1 -12 -1 -1 +12 +1 +1 -1 +1 -1 +1 A 2.0 -0.3 -1 -1 -10 Min Max 2.4 0.4 VCC + 0.3 0.8 +1 +1 -1 +1 2.0 -0.3 -1 -12 Min Max 2.4 0.4 VCC + 0.3 0.8 +1 -15 Min Max Unit V V V V A
Output HIGH Voltage VCC = Min, IOH = -4.0 mA Output LOW Voltage VCC = Min, IOL = 8.0 mA Input HIGH Voltage Input LOW Voltage[3] Input Leakage Current
Note 3. VIL (min) = -2.0V and VIH(max) = VCC + 0.5V for pulse durations of less than 20 ns.
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CY7C1021CV33
Capacitance
Tested initially and after any design or process changes that may affect these parameters. Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max 8 8 Unit pF pF
Thermal Resistance
Tested initially and after any design or process changes that may affect these parameters. Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51 SOJ 65.06 34.21 TSOP II 76.92 15.86 FBGA 95.32 10.68 Unit C/W C/W
JA JC
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [4]
8-ns devices: OUTPUT 50 * CAPACITIVE LOAD CONSISTS OF ALL COMPONENTS OF THE TEST ENVIRONMENT 1.5V 10-, 12-, 15-ns devices: Z = 50 3.3V
R 317
30 pF*
OUTPUT
30 pF*
R2 351
(a)
(b)
High-Z characteristics: R 317 3.0V 90% GND 10% ALL INPUT PULSES 90% 10% 3.3V OUTPUT 5 pF R2 351
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
Note 4. AC characteristics (except High-Z) for all 8-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
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CY7C1021CV33
Switching Characteristics
Over the Operating Range [5] Parameter Read Cycle tpower[6] tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU[9] tPD[9] tDBE tLZBE tHZBE Write Cycle tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE tBW
[10]
Description
-8 Min 100 8 8 3 8 5 0 4 3 4 0 8 5 0 4 8 7 7 0 0 6 5 0 3 4 6 7 10 8 8 0 0 7 5 0 3 0 0 3 0 3 Max Min 100 10
-10 Max Min 100 12 10 3 10 5 0 5 3 5 0 10 5 0 5 12 9 9 0 0 8 6 0 3 5 8
-12 Max Min 100 15 12 3 12 6 0 6 3 6 0 12 6 0 6 15 10 10 0 0 10 8 0 3 6 9
-15 Max
Unit
VCC(Typical) to the First Access Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low Z OE HIGH to High CE HIGH to High
[7]
s ns 15 15 7 7 7 15 7 7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7 ns ns
Z[7, 8] Z[7, 8]
CE LOW to Low Z[7] CE LOW to Power Up CE HIGH to Power Down Byte Enable to Data Valid Byte Enable to Low Z Byte Disable to High Z Write Cycle Time CE LOW to Write End Address Setup to Write End Address Hold from Write End Address Setup to Write Start WE Pulse Width Data Setup to Write End Data Hold from Write End WE HIGH to Low Z[7] WE LOW to High Z[7, 8] Byte Enable to End of Write
Notes 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V. 6. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed. 7. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 8. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of "AC Test Loads and Waveforms" on page 5. Transition is measured 500 mV from steady state voltage. 9. This parameter is guaranteed by design and is not tested. 10. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE is LOW to initiate a write. The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
Document Number: 38-05132 Rev. *I
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CY7C1021CV33
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled)[11, 12]
tRC RC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Figure 5. Read Cycle No. 2 (OE Controlled)[12, 13]
ADDRESS tRC CE tACE OE tDOE BHE, BLE tLZOE tDBE tLZBE DATA OUT VCC SUPPLY CURRENT HIGH IMPEDANCE tLZCE tPU 50% tHZCE tHZBE DATA VALID tPD 50% ICC ISB tHZOE
HIGH IMPEDANCE
Notes 11. Device is continuously selected. OE, CE, BHE, and/or BLE = VIL. 12. WE is HIGH for read cycle. 13. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05132 Rev. *I
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CY7C1021CV33
Switching Waveforms
(continued) Figure 6. Write Cycle No. 1 (CE Controlled)[14, 15]
tWC ADDRESS
tSA CE tAW
tSCE
tHA tPWE
WE tBW BHE, BLE tSD DATA IO tHD
Figure 7. Write Cycle No. 2 (BLE or BHE Controlled)
tWC ADDRESS
tSA BHE, BLE
tBW
tAW tPWE WE tSCE CE tSD DATA IO tHD
tHA
Notes 14. Data IO is high impedance if OE, BHE, and/or BLE= VIH. 15. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.
Document Number: 38-05132 Rev. *I
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CY7C1021CV33
Switching Waveforms
(continued) Figure 8. Write Cycle No. 3 (WE Controlled, LOW)
tWC ADDRESS
tSCE CE tAW tSA WE tBW BHE, BLE tPWE
tHA
tHZWE DATA IO
tSD
tHD
tLZWE
Truth Table
CE H L OE X L WE X H BLE X L L H L X L L L H L L H X H X X H BHE X L H L L H L X H IO1 - IO8 IO9 - IO16 High Z Data Out Data Out High Z Data In Data In High Z High Z High Z High Z Data Out High Z Data Out Data In High Z Data In High Z High Z Mode Power Down Read - All Bits Read - Lower Bits Only Read - Upper Bits Only Write - All Bits Write - Lower Bits Only Write - Upper Bits Only Selected, Outputs Disabled Selected, Outputs Disabled Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Power Standby (ISB)
Document Number: 38-05132 Rev. *I
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CY7C1021CV33
Ordering Information
Speed (ns) 8 10 Ordering Code CY7C1021CV33-8BAXC CY7C1021CV33-10VXC CY7C1021CV33-10ZXC CY7C1021CV33-10BAXI CY7C1021CV33-10ZSXA 12 CY7C1021CV33-12ZXC CY7C1021CV33-12BAI CY7C1021CV33-12VXE CY7C1021CV33-12ZSXE 15 CY7C1021CV33-15ZXC CY7C1021CV33-15ZSXA Package Diagram 51-85096 48-ball FBGA (Pb-free) 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) 51-85087 44-pin TSOP Type II (Pb-free) 51-85096 48-ball FBGA (Pb-free) 51-85087 44-pin TSOP Type II (Pb-free) 51-85087 44-pin TSOP Type II (Pb-free) 51-85096 48-ball FBGA 51-85082 44-pin (400-Mil) Molded SOJ (Pb-free) 51-85087 44-pin TSOP Type II (Pb-free) 51-85087 44-pin TSOP Type II (Pb-free) 51-85087 44-pin TSOP Type II (Pb-free) Commercial Automotive-A Industrial Automotive-A Commercial Industrial Automotive-E Package Type Operating Range Commercial Commercial
The 44 pin TSOP II package containing the Automotive grade device is designated as "ZS", while the same package containing the Commercial/Industrial grade device is "Z".
Document Number: 38-05132 Rev. *I
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CY7C1021CV33
Package Diagrams
Figure 9. 44-Pin (400 Mil) Molded SOJ
51-85082-*B
Document Number: 38-05132 Rev. *I
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CY7C1021CV33
Package Diagrams
(continued) Figure 10. 44-Pin Thin Small Outline Package Type II
51-85087-*A
Document Number: 38-05132 Rev. *I
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CY7C1021CV33
Package Diagrams
(continued) Figure 11. 48-Ball FBGA (7 x 7 x 1.2 mm)
TOP VIEW
BOTTOM VIEW PIN 1 CORNER O0.05 M C O0.25 M C A B O0.300.05(48X)
PIN 1 CORNER (LASER MARK) 12 A B C 7.000.10 5.25 D E F G H 7.000.10 0.75 3 4 5 6
6
5
4
3
2
1 A B C D E
2.625
F G H
A
A
1.875 0.75
B
7.000.10 3.75 B 7.000.10
0.530.05
0.25 C
0.15(4X) 0.210.05 0.10 C
SEATING PLANE 0.36 C
1.20 MAX.
51-85096-*G
Document Number: 38-05132 Rev. *I
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CY7C1021CV33
Document History Page
Document Title: CY7C1021CV33, 1-Mbit (64K x 16) Static RAM Document Number: 38-05132 REV. ** *A *B *C *D *E *F ECN NO. 109472 115044 115808 120413 238454 334398 493565 Issue Date 12/06/01 05/08/02 06/25/02 10/31/02 See ECN See ECN See ECN Orig. of Change HGK HGK HGK DFP RKF SYT NXR New datasheet Ram7 version C4K x 16 Async Removed "Preliminary" ISB1 and ICC values changed Updated BGA pin E4 to NC 1) Added Automotive Specifications to datasheet 2) Added Pb-free devices in the Ordering Information Added Pb-free on page 9 and 10 Added Automotive-A operating range Corrected typo in the Pin Definition table Changed the description of IIX from Input Load Current to Input Leakage Current in DC Electrical Characteristics table Removed IOS parameter from DC Electrical Characteristics table Updated the ordering information table Added tPOWER specification in the AC Switching Characteristics table Added footnote 8 Description of Change
*G *H *I
563963
See ECN
VKN
1390863 See ECN VKN/AESA Corrected TSOP II package outline 1891366 See ECN VKN/AESA Added -10ZSXA part in the Ordering Information table Updated Ordering Information Table
(c) Cypress Semiconductor Corporation, 2001-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-05132 Rev. *I
Revised January 04, 2008
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